Comparative studies on electrical bias temperature instabilities of In–Ga–Zn–O thin film transistors with different device configurations

• In–Ga–Zn–O based oxide semiconductor thin-film transistors.
• Systematic comparisons between the top- and bottom-gate structures.
• Positive bias temperature stabilities and related mechanisms.
• Proposal of promising device reliabilities for the top-gate IGZO TFTs.
• Feasibility for the highly performance backplane devices for next-generation displays.

We investigated the effect of positive bias temperature stress (PBTS) on the device stabilities of In–Ga–Zn–O thin film transistors with bottom gate and top gate structures. Under the PBTS conditions at the gate voltage of +20 V and the temperature of 60 °C, the turn-on voltage experienced a negative shift of −1.5 V for the top gate device, while a larger positive shift of 3.0 V was observed for the bottom gate device. From the variations in transfer characteristics at various temperatures and the discussions on the thermal activation energy, it was suggested that these different behaviors of two devices originated from interface trap densities caused by the plasma damage and the pinning of Fermi energy level for the bottom and top gate devices, respectively. It was very encouraging that the variation of the turn-on voltage could be minimized when the top gate device was fabricated to have a very controlled interface.