An embedded nonvolatile memory cell with spacer floating gate for power management integrated circuit applications

• A new nonvolatile memory cell with a spacer poly-Si floating gate is demonstrated.
• A 0.35 μm 20-V class high-voltage CMOS process is applied for fabrication.
• A floating gate is buried under a LDD oxide; thus the channel length can be scaled.
• The proposed cell shows good endurance, disturbance and retention characteristics.

This paper describes a simple nonvolatile memory cell with a poly-Si spacer floating gate for power management integrated circuit applications. The proposed memory cell is fabricated using a 0.35 μm double-poly high-voltage CMOS process which includes PIP capacitor, LV (5 V), and HV (20 V) CMOS devices. The floating gates of the proposed cell are buried under a LDD spacer oxide; thus the unit cell can be scaled easily in the channel length direction. In addition, any extra photo masking step is not required for the proposed cell in the applied fabrication process. The proposed cell shows an acceptable threshold voltage window of up to 104 cycles and less than 2% threshold voltage shifts in an 85 °C retention test.