Gate leakage current partitioning in nanoscale double gate MOSFETs, using compact analytical model

This paper presents a compact gate leakage current partitioning model for nanoscale Double Gate (DG) MOSFETs, using analytical models of the direct tunneling gate leakage current. Gate leakage current becomes important and an essential aspect of MOSFET modeling as the gate oxide thickness is scaled down to 1 nm and below in advanced CMOS processes. We considered an ideal interface (ideal case without an interfacial layer) and two layers high k dielectric materials as gate insulators. In the case of two layers, a thin layer of SiO2 as an interfacial layer is considered. The results of the gate current partitioning components into drain and source show good agreement with 2D TCAD numerical device simulation (Silvaco Atlas).

► We presented a model of the gate current partitioning into the source and drain for a DG MOSFETs structure.
► Model based on a compact analytical gate leakage current which includes short channel effects.
► The influence and impact of the thickness of the interfacial SiO2 layer on the gate-drain and gate-source components has been shown.
► Model works well from the numerical simulation (Silvaco Atlas) point of view.
► Model addresses the impact of the gate current on the device/circuit performance.