Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs

Drain bias stress effects on amorphous Zinc Indium Oxide (a-ZIO) Thin Film Transistors (TFTs) are important in flexible electronic systems. The drain bias impacts the overall threshold voltage (Vth) shift more so in the saturation stress mode than in the linear stress mode. Localization of degradation region in channel results in asymmetry in post stressed drain current in forward and reverse operations. This brief studies the impact of drain bias on Vth degradation, and also the effect on post stressed forward and reverse currents in a-ZIO TFTs, under both positive and negative gate bias stress in different regions of operation. Based on the measured results, an empirical expression incorporating drain bias effect on Vth degradation is derived. Also the measured results point to charge trapping in the insulator–semiconductor interface as the dominant degradation mechanism.

► This paper studies the impact of drain bias stress, under fixed gate bias in a-IZO TFTs.
► The change in VT is more for higher drain bias.
► Both subthreshold slope and transfer characteristics change but recover when left unstressed.
► The degradation follows logarithmic model, associated with charge trapping.
► All observations point to charge trapping as degradation mechanism.