High mobility CMOS: First demonstration of planar GeOI p-FETs with SOI n-FETs

We report for the first time the fabrication and the electrical operation of a Ge and Si based CMOS planar scheme with GeOI pFETs and SOI nFETs, taking advantage of the best mobility configuration for holes (Ge) and electrons (Si). The hybrid Ge/Si wafers have been obtained by the local Ge enrichment technique on SOI wafers. A sub 600 °C CMOS transistor process featuring High-K/Metal Gate and silico-germanidation was used to obtain functional high mobility CMOS transistors (down to L = 160 nm). Excellent low-field mobility values for electrons in Si nFETs and holes in Ge pFETs were achieved (275 and 142 cm2/V/s resp.).

Research highlights
► Ge and Si areas were obtained on SOI wafers thanks to the Ge enrichment technique.
► DualChannel Ge–Si CMOS is demonstrated with a sub 600 °C Fully Depleted process.
► Planar GeOI pFETs and SOI nFETS with High-K metal-gate were cointegrated.
► This DualChannel Ge–Si CMOS exhibit the best hole/electron mobility configuration.
► The simultaneous salicidation and germanidation minimize the CMOS access resistance.