Gate-edge charges related effects and performance degradation in advanced multiple-gate MOSFETs

► Effect of process-induced negative charges at the gate edges on MOSFETs performance. ► NCs at the gate edges can degrade subthreshold behavior and analog FoM of MOSFET. ► Enhanced Gmmax and apparent better SCE control can be due to NCs at the gate edges. ► Such behavior may appear in any advanced technology employing novel gate stacks. ► Complete set of device characteristics is required for a fair technology assessment.