Capacitor-less A-RAM SOI memory: Principles, scaling and expected performance

Based on numerical TCAD simulations, the novel capacitor-less A-RAM memory cell is detailed in terms of electrostatic effects, transient operation and retention time. The particular double-body device architecture on SOI is beneficial for better scalability than conventional 1T-DRAMs. Its dual body partitioning suppresses the supercoupling effect in SOI; the two types of carriers can coexist inside ultrathin fully depleted transistors. Electrons and holes are accommodated in different bodies, separated by an insulator layer, but remain electrostatically coupled. A-RAM features easy discrimination of ‘0’ and ‘1’ states, simple control waveforms and very promising performance.

Research highlights
► We present a novel capacitor-less single-transistor memory cell.
► The cell features a body partitioning for hole storage and electron current.
► The scalability benefits from an enhanced potential difference between interfaces.
► The cell shows attractive performance in terms of current margins and retention time.