Simulation of the electrostatic and transport properties of 3D-stacked GAA silicon nanowire FETs

In this work, both the electrostatic and transport features of 3D-stacked Gate-all-Around silicon nanowires are studied using simulations based on a self-consistent solution of the two-dimensional Poisson and Schrödinger equations. A comprehensive analysis of the effect of the strain induced by the fabrication process of such devices is carried out and a comparison made with a reference trigate device. It is shown that stacked nanowires can be a good alternative to trigate MOSFETs for sub-22 nm technology nodes, due to the increased gate electrostatic control of the channel of the Gate-all-Around architecture and to the higher total charge that can be achieved for the same wafer surface. It is also shown that the electron mobility calculated for unstrained stacked NWs is lower than that of trigate devices, but the strain induced in the channels by the SiGe layers during the fabrication process of stacked NWs can overturn this situation.

Research highlights
► We studied the electrostatic and transport properties of stacked nanowires (SNWs).
► We compared SNWs to a reference trigate transistor with similar dimensions.
► The calculated Nt in stacked NWs and trigates depends on the overall perimeter of the devices.
► The phonon-limited mobility shows a strong dependence on the WSi/HSi ratio.
► The electron mobility of stacked NWs depends on the biaxial strain induced during the fabrication process.