Electrical characterization of Si nanowire field-effect transistors with semi gate-around structure suitable for integration

Silicon nanowire (Si NW) field-effect transistors with a semi gate-around structure suitable for integration have been fabricated using conventional CMOS processes. With the use of SiO2 pedestal and SiN sidewall, lithography and etching steps over NW can easily realized. A subthreshold slope (SS) of 71 mV/dec. with ION/IOFF > 105 and a high on-current of 49.6 μA at Vg–Vth = 1.0 V have been obtained with a 25-nm-wide Si NW FET with a gate length and oxide thickness of 200 and 5 nm, respectively. Normalization of the on-current by peripheral length of Si NW FET from 25 to 45 nm in width has revealed comparable current density, which suggests that carriers are formed at the periphery of NW. The effective electron mobility of Si NW FETs has been revealed to be comparable to that of planar FET, indicating negligible process induced damages. The proposed process has a high potential for Si NW FET for large scale integration.