Theoretical analysis of the vertical LOCOS DMOS transistor with process-induced stress enhancement

This work presents a theoretical analysis, validated by numerical simulations, of the vertical LOCOS DMOS structure. New analytical models of the specific on-state resistance and breakdown voltage are developed, which improve upon previous models in that an explicit dependence on device geometry and impurity concentration is worked out. The model accounts for the space charge due to the lateral and vertical depletion regions related to the field plates and the p-body/n-drift junction, respectively. The process-induced strain within the drift region is modeled as a function of the main geometrical parameters. Vertical LOCOS DMOS devices can thus be easily optimized, as shown by a few examples.