A comparison of advanced transport models for the computation of the drain current in nanoscale nMOSFETs

Template devices representative of 22 nm Double-Gate and 32 nm Single-Gate Fully-Depleted Silicon-On-Insulator transistors were used as a common benchmark to highlight the differences between the quantitative predictions of different approaches. Using the standard scattering and mobility models for unstrained silicon channels and pure SiO2 dielectrics, the predictions of the different approaches for the 32 nm template are quite similar. Simulations of the 22 nm device instead, are much less consistent, particularly those achieved with MC simulators. Comparison with experimental data for a 32 nm device shows that the modeling approach used to explain the mobility reduction induced by the high-κ dielectric is critical. In the absence of a clear understanding of the impact of high-κ stack on transport, different models, all providing agreement with the experimental low-field mobility, predict quite different drain currents in saturation and in the sub-threshold region.