Substrate current characterization and optimization of high voltage LDMOS transistors

A 30-V LDMOS integrated with a standard 0.15 μm CMOS process is investigated for its double-hump substrate current (Ib) characteristics. The origin of this abnormal second substrate current hump is explained by Kirk effect. The impact of this second hump of Ib on reliability and device performance is observed. An analytical expression for the second hump of Ib is established by calculating the impact ionization in the drift region according to the electric field distribution obtained by solving Poisson’s equation. The calculated results are compared against the silicon data under various gate/drain bias voltages showing excellent consistency. Additionally, based on the derived expressions for substrate current, the process parameters are optimized achieving much lower substrate current and better reliability performance.