کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
753498 | 895538 | 2007 | 8 صفحه PDF | دانلود رایگان |
![عکس صفحه اول مقاله: Scaling issues for analogue circuits using Double Gate SOI transistors Scaling issues for analogue circuits using Double Gate SOI transistors](/preview/png/753498.png)
This work presents a systematic analysis on the impact of source–drain engineering using gate “non-overlapped” on the RF performance of nano-scaled fully depleted Double Gate SOI transistors, when used in the design of a typical two stage Operational Transconductance Amplifier (OTA). It is evident that for a gate length less than 40 nm, the incorporation of optimal source–drain engineering requiring a spacer length, which may exceed the length of the gate, is particularly beneficial in analogue applications. Lengthening the spacer reduces gate capacitance in the weak/moderate inversion region more than transconductance, improving cut-off frequency fT. This improvement is particularly significant in a circuit application where an optimal spacer of 1.5 times the gate length is proposed. This gate under-lapped concept with extended spacer can also significantly enhance DC gain of the OTA, by increasing the Early Voltage, while maximising the transconductance to current ratio in the weak to moderate inversion, close to threshold voltage. With optimally designed devices, the sensitivity of OTA circuit performance to doping profile is shown to be relatively low.
Journal: Solid-State Electronics - Volume 51, Issue 2, February 2007, Pages 320–327