Parasitic memory effects in shallow-trench-isolated nanocrystal memory devices

This paper examines the influence of channel edge effects on the memory performance of shallow-trench-isolated Si-nanocrystal single-MOSFET memory cells. The devices were fabricated in a manufacturing environment using a process flow and design rules based on a 0.15 μm Flash-EEPROM technology. The Si-nanocrystals were generated in the gate oxide by low-energy (1 keV) ion-beam-synthesis. For 10 × 10 μm2 and 0.9 × 0.6 μm2 (W × L) devices, parasitic transistors formed at the channel edges lead to a “subthreshold hump” in the transfer characteristics. Beyond this current hump, the device transfer characteristics correspond to that of the intrinsic transistor formed in the central part of the channel. Memory testing reveals that the parasitic transistors can be programmed or erased but exhibit memory characteristics significantly different than that of the intrinsic transistor. Hence, the extracted memory windows strongly depend on the source-drain current used for threshold-voltage evaluation when applying the constant current method. In addition to the latter method, the more accurate transconductance change method is herein applied to describe the memory behavior of the intrinsic and parasitic transistors in a more comprehensive way. Finally, while no “subthreshold hump” appears in the transfer characteristics of 0.16 × 0.3 μm2 transistors, it is shown that the parasitic transistors remain active and their operation dominates the memory behavior of the devices. As emphasized herein the parasitic transistors affect drastically the memory performance of the intended devices and this detrimental effect could constitute a technological issue towards the integration of nanocrystal floating-gate in conventional memory architecture.