کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
8163852 | 1525662 | 2018 | 4 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Level shifting circuit for hybrid superconductor-to-semiconductor interface
ترجمه فارسی عنوان
مدار تغییر سطح برای رابط ابررسانایی به نیمه هادی هیبریدی
دانلود مقاله + سفارش ترجمه
دانلود مقاله ISI انگلیسی
رایگان برای ایرانیان
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
فیزیک و نجوم
فیزیک ماده چگال
چکیده انگلیسی
Memory circuits based on superconductivity electronics by the presence of very high speed of switching and extremely low consumption of power have no suitable density. For this purpose, the hybrid circuit of superconductor-semiconductor was proposed. The main idea of this circuit is concentration on using the advantages of each one of two technologies. In construction of memory circuits, designing an interface hybrid circuit of superconductor-semiconductor is considered as a big challenge, because this circuit should reach very weak signals of SFQ in output of circuit based on superconductor technology with low delay time of issue to suitable levels for applying to semiconductor circuit. Our proposed circuit is an amplifier including two stages. In the first stage, we use a memory circuit with Josephson junction as the name of Super Stack including Suzuki Stack series. This circuit changes 6Â mV input to a few tens mV and we lower voltage level towards similar circuits by declining the number of Josephson junctions in each Suzuki Stack. The second stage of a circuit is latch comparator in semiconductor technology that receives its input from the output of first stage and reaches it to the limit of Volt level. In the first stage two Suzuki stacks were employed producing a 60Â mV output with a propagation delay of 23Â ps which represents a 51% improvement in speed compared with other topologies reported in the literature with similar output amplitudes. In the second stage, 16Â nm graphene nano-ribbon transistors MOS-GNRFETs were used and the results were compared with those obtained based on CMOS 16Â nm LP and CMOS HP transistors. Simulations indicated that the power delay product (PDP) is lower using graphene nano-ribbon transistors as compared with 16Â nm CMOS LP and HP transistors by 54% and 79%, respectively. Furthermore, power consumption was lower for the topology employing MOS-GNRFETs as compared with those using 16Â nm CMOS LP and HP devices by 47.2% and 78%, respectively. The speed performance is also discussed.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Physica C: Superconductivity and its Applications - Volume 552, 15 September 2018, Pages 57-60
Journal: Physica C: Superconductivity and its Applications - Volume 552, 15 September 2018, Pages 57-60
نویسندگان
F. Aghighi, S. Jamasb, M. Mazaheri,