Influence of spacer layer on InP/InGaAs δ-doped heterojunction bipolar transistors

In this paper, the influence of spacer layers on DC performance of InP/InGaAs δ-doped heterojunction bipolar transistors (HBT's) is investigated by theoretical analysis and experimental results. As compared to previous δ-doped HBT's, the studied device has another left-side InGaAs spacer added between δ-doped sheet and InP emitter layers at base-emitter (B-E) junction. The left-side spacer more effectively helps to maintain the integrity of uniform-doped InP emitter and the quality of interface; reduce the emitter barrier for electrons, decrease the collector-emitter offset voltage, and increases the confinement effect for holes. An analytical model related to the potential spike at B-E junction and base recombination current is developed to demonstrate the transistor performances. Experimentally, transistor performances with a maximum current gain of 455 and a low offset voltage of 55 mV are achieved.