Analysis of a rapidly reconfigurable multicast capable photonic switched interconnect

We present a complete mathematical formalism for a rapidly reconfigurable gated timeslot tuner based on a serial feed-forward structure. This gated serial timeslot tuner has been a key component for various demonstrations including a 100 Gb/s photonic switched interconnect [K.-L. Deng, R.J. Runser, P. Toliver, I. Glesk, P.R. Prucnal, J. Lightwave Technol. 18 (2000) 1892]. Design constraints for the proper operation of the interconnect are developed. Methods to predict feasible multicast combinations and control patterns required for driving the timeslot tuner are presented in terms of a two-dimensional (2D) contour map.