کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
9817752 | 1518771 | 2005 | 7 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Transistor challenges - A DRAM perspective
دانلود مقاله + سفارش ترجمه
دانلود مقاله ISI انگلیسی
رایگان برای ایرانیان
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی مواد
سطوح، پوششها و فیلمها
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Transistor challenges - A DRAM perspective Transistor challenges - A DRAM perspective](/preview/png/9817752.png)
چکیده انگلیسی
Key challenges of the transistor scaling from a DRAM perspective will be reviewed. Both, array transistors as well as DRAM support devices face challenges that differ essentially from high performance logic device scaling. As a major difference, retention time and standby current requirements characterize special boundary conditions in the DRAM device design. Array device scaling is determined by a chip size driven aggressive node scaling. To continue scaling, major innovations need to be introduced into state-of-the-art planar array transistors. Alternatively, non planar device concepts will have to be evaluated. Support device design for DRAMs is driven by today's market demand for increased chip performances at little to no extra cost. Major innovations are required to continue that path. Besides this strive for performance increase, special limitations for “on pitch” circuits at the array edge will come up due to the aggressive cell size scaling.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms - Volume 237, Issues 1â2, August 2005, Pages 228-234
Journal: Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms - Volume 237, Issues 1â2, August 2005, Pages 228-234
نویسندگان
Juergen W. Faul, Dietmar Henke,