Optimization of a very cost-effective high voltage p-channel transistor implemented in a standard twin-tub CMOS technology

This paper discusses the optimization and fabrication of a high voltage p-channel extended drain MOSFET (ED-pMOSFET) using standard low cost 2.5 μm twin-tub CMOS technology for digital applications, with only one extra processing step. The ED-pMOSFET transistor has been optimized using 2D simulators attending both specific on-resistance and breakdown voltage. Extended drain ED-pMOSFET transistors with low specific on-resistance (active area) Ron = 6.0 mΩ cm2 (at VG = −5 V) and breakdown voltage of 36 V have been implemented demonstrating competitive performance values with other p-channel devices previously reported in more sophisticated technologies. The proposed device along with n-channel LDMOS high voltage devices and the standard low voltage CMOS devices, constitute a full smart power CMOS technology that can reach breakdown voltages up to 50 V and currents up to 1 A.