Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities

We review the main issues in scaling down the interpoly dielectric (IPD) for future floating gate Flash memory technology generations. The equivalent oxide thickness (EOT) of the IPD must reach the sub-10 nm range to enable lowering of the operating voltages and further scale device feature sizes. Additionally, the loss of control gate wrap around the floating gate for high density memories as device dimensions scale down will require a drastic reduction (up to 60%) in IPD EOT to maintain the same capacitive coupling. As the scalability of the conventional oxide-nitride-oxide (ONO) IPD's is limited, we propose new solutions that exploit the opportunities offered by the high-κ dielectrics. Their effectiveness increases when midgap and p-type metals are considered, instead of the conventional polysilicon control gate. The optimal approach depends on the most critical requirement that the IPD has to fulfill, which in turn is application or device-structure dependent. The nonideal nature of the dielectric materials, however, may severely reduce the design window, calling for a sustained effort to improve their electrical properties by process optimization.