Tuning tunnel barrier in Si3N4-based resistive memory embedding SiO2 for low-power and high-density cross-point array applications

• SiN-based RRAM with selector function was proposed.
• Resistive switching behaviors was investigated depending on tunnel barrier thickness.
• Nonlinearity was modulated by compliance, read voltage, and SiO2 thickness.
• Low current operation ensures high selectivity.

In this paper, nonlinear and low-power resistive switching characteristics of Si3N4-based RRAM embedding SiO2 tunnel barrier (TB) with full compatibility to conventional Si CMOS processing have been extensively studied to solve crosstalk issue in a cross-point structure. It is found that the nonlinear characteristics of a simple metal-insulator-insulator-silicon (MIIS) structure are mainly attributed to two different tunneling mechanisms in the SiO2 layer. Furthermore, we offer an optimized solution by modulating compliance current (ICC), read voltage (VREAD), and TB thickness for higher selectivity. Low current operation tuned by ICC, VREAD, and TB thickness is essential to achieve higher selectivity for low-power and high-density cross-point array applications.

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