Anatomizing the Impact of High Dielectric Gate Materials on the Charge Transport in Graphene Field Effect Transistors

We have investigated the impact of different dielectric materials as gate dielectric in ZAZ structures for a particular width and central region using density functional theory (DFT) with self–consistent calculations within the framework of Non-Equilibrium Green Function (NEGF) by using Krylov methods as self-energy calculator in ATK 13.8.0. The length of the channel separation and width is taken to be 4 and 6 respectively. In this case we only varied the left electrode voltage and kept right electrode voltage to be zero so that net effect of the VDS can be observed. The VDS is varied by keeping all the parameters constant and then the graphs are plotted for IV curves, differential conductance (dI/dV). The distinct changes in conductance and I-V curves reported as the material of gate dielectric was varied for low-κ dielectrics like 2,4, 8 as well as high-κ dielectrics like 18,20,25 etc. at different bias voltages from -2V to 2 V with steps of 0.5 V. From the simulated results we observed that the maximum conductance reported for high dielectrics 25 (CeO2) is in the range of 10-5 siemens whereas the maximum conductance reported for low dielectrics 4(SiO2) is in the range 10-6 siemens through Z-A-Z (GFET) structures for positive bias voltages.