Impedance model of electrolyte–insulator–semiconductor structure with porous silicon semiconductor

We present a generic impedance model for the porous silicon|electrolyte structure that is valid for a range of interfacial layers and bias in these structures. The model is validated using three widely different porous structures: short irregular silicon columns and pores, long cylindrical silicon columns and pores; and branched interconnected silicon microchannels and voids in a mesh structure. The model incorporates appropriate RC or constant phase elements for the different parts of the porous structure, namely, the top of the silicon columns (channels)|electrolyte, the column (channel) walls|electrolyte in the pores/channels, and the electrolyte|semiconductor interface at the base of the pores/channels. This physical model underscores the effects of column/channel depletion and accumulation, either due to applied bias or change of surface charge, to the impedance spectra of the device. The model helps to explain why the porosity needs to be optimized for specific applications and helps as a measurement tool for optimization.