Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels

Shorter global interconnects enable 3D NoC structures to offer higher performance, improved packaging density, and lower interconnect power consumption to CMPs and SoCs compared to their 2D counterparts. However, substantial challenges such as high peak temperatures, power densities and area footprints of vertical interconnects in each layer cannot be ignored. In this paper, a power and area efficient 3D NoC architecture based on power-aware Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate these challenges. Instead of using a pair of unidirectional channels for inter-layer communication, utilizing a dynamically self-configurable BBVC enables a system to benefit from low-latency nature of the vertical interconnects. In addition, based on the GALS implementation approach of the proposed channels, a forecasting-based dynamic frequency scaling technique for reducing the power consumption of the inter-layer communication is introduced. Simulation results show that the proposed architecture can reduce up to 47% through-silicon via (TSV) area footprint and up to 18% NoC power consumption with a slight performance degradation compared to a typical Symmetric 3D NoC.

► A power and area efficient 3D NoC architecture is presented.
► We replace unidirectional vertical channels by Bidirectional Bisynchronous Vertical Channels.
► We present a forecasting-based DFS technique to manage TSV power consumption.
► The interconnect TSV area footprint is reduced (up to 47%).
► The NoC power consumption is saved (up to 18%).