Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers

Codes that have large-stride/irregular-stride (L/I) memory access patterns, e.g., sparse matrix and linked list codes, often perform poorly on mainstream clusters because of the general purpose processor (GPP) memory hierarchy. High performance reconfigurable computers (HPRC) contain both GPPs and field programmable gate arrays (FPGAs) connected via a high-speed network. In this research, simple 64-bit floating-point codes are used to illustrate the runtime performance impact of L/I memory accesses in both software-only and FPGA-augmented codes and to assess the benefits of mapping L/I-type codes onto HPRCs. The experiments documented herein reveal that large-stride software-only codes experience severe performance degradation. In contrast, large-stride FPGA-augmented codes experience minimal performance degradation. For experiments with large data sizes, the unit-stride FPGA-augmented code ran about two times slower than software. On the other hand, the large-stride FPGA-augmented code ran faster than software for all the larger data sizes. The largest showed a 17-fold runtime speedup.

► Codes with large stride/irregular stride (L/I) memory access patterns perform poorly on clusters.
► This poor performance is due to GPP memory hierarchy. Our research shows FPGA do not suffer from this.
► Thus, L/I-type codes may have an affinity for high performance reconfigurable computers (HPRCs).
► Mapping two simple algorithms onto FPGA-based HPRC clusters were presented to illustrate this idea.
► Experiments reveal that the large-stride FPGA-augmented code ran faster than software by 17-fold.