Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors

• Circuit switching and packet switching are both provided in the HCS network with a hybrid scheme.
• The channel preserver provides circuit switching by actively analyzing the packet head info.
• The router in the HCS network is a buffer-less design, and a packet is transferred in a pipelined manner.
• An AMBA wrapper is implemented to enable the on-chip network to behave like a bus for AMBA IPs.
• Burst and locked transmissions are provided based on the circuit-switched scheme.

Large-scale chip-multiprocessors (CMPs) need a scalable communication structure characterized by low cost, low power, and high performance to meet their on-chip communication requirements. This paper presents a hybrid circuit-switched (HCS) network for on-chip communication in the large-scale CMPs. The HCS network, which is Advanced Microcontroller Bus Architecture (AMBA) compatible, is composed of bufferless switches, pipeline channels, and network interfaces. Furthermore, packets are transferred in a hybrid transmission scheme. If a message has only one packet, the transmission scheme for this message is packet switching. Conversely, if a message contains multiple packets, the transmission scheme for this message is circuit switching. We evaluate HCS networks with different channel depths and then compare the HCS network with the Stanford elastic buffer (EB) network. Our results show that the HCS network with two-depth channel requires 83% less power and occupies 32% less area compared with the EB network. Furthermore, under maximum frequency and single traffic, the HCS network with two-depth channel provides 37% lower zero-load latency, 390% higher maximum throughput per unit power, and 19% higher maximum throughput per unit area compared with the EB network.