C-AMTE: A location mechanism for flexible cache management in chip multiprocessors

This paper describes Constrained Associative-Mapping-of-Tracking-Entries (C-AMTE), a scalable mechanism to facilitate flexible and efficient distributed cache management in large-scale chip multiprocessors (CMPs). C-AMTE enables fast locating of cache blocks in CMP cache schemes that employ one-to-one or one-to-many associative mappings. C-AMTE stores in per-core data structures tracking entries to avoid on-chip interconnect traffic outburst or long distance directory lookups. Simulation results using a full system simulator demonstrate that C-AMTE achieves improvement in cache access latency by up to 34.4%, close to that of a perfect location strategy.

Research highlights
► C-AMTE enables fast location of cache blocks without swamping the NoC.
► C-AMTE can be applied whenever associative mapping is used for cache blocks.
► C-AMTE can be applied either in case of one-to-one or one-to-many mapping.
► C-AMTE can be applied to cache designs that extend the private or shared schemes.
► C-AMTE opens opportunities for architects to propose creative cache designs.