کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4951551 | 1441479 | 2017 | 23 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A low-area unified hardware architecture for the AES and the cryptographic hash function Grøstl
دانلود مقاله + سفارش ترجمه
دانلود مقاله ISI انگلیسی
رایگان برای ایرانیان
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
نظریه محاسباتی و ریاضیات
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
This article describes the design of a compact 8-bit coprocessor for the Advanced Encryption standard (AES) (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl. Our Arithmetic and Logic Unit has only one instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security (i.e. 128-, 192-, and 256-bit encryption keys; 256- and 512-bit message digests). A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput (up to 217 Mbits/s and 92 Mbits/s for encryption and hashing, respectively). The proposed coprocessor is well-suited for resource-constrained embedded systems, where several security protocols rely only on block ciphers and hash functions. One can exploit the design philosophy presented in this paper in order to design a unified architecture for other algorithms.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Journal of Parallel and Distributed Computing - Volume 106, August 2017, Pages 106-120
Journal: Journal of Parallel and Distributed Computing - Volume 106, August 2017, Pages 106-120
نویسندگان
Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki,