کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4951553 | 1441479 | 2017 | 11 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
DSPONE48: A methodology for automatically synthesize HDL focus on the reuse of DSP slices
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
نظریه محاسباتی و ریاضیات
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چکیده انگلیسی
This work proposes a methodology to synthesize arithmetic operations maximizing the reuse of the DSP48E1 blocks presented in the new reconfigurable architectures. The input for DSPONE48 is a VHDL code without any reference to the FPGA hardware resources. This input code is modified, so the synthesis tool is able to implement it with DSP slices. In order to achieve this objective we use DSP block instantiation templates and we encourage the use of SIMD mode within the DSP block. This methodology replaces automatically the most common arithmetic operations by their equivalents on DSP slices. The methodology guarantees that the new code preserves the functionality and the number of execution cycles of the original design. Experimental results, on a Virtex 7 FPGA, show that the designs obtained by DSPONE48 use less DSPs than those obtained automatically by Xilinx ISE or Vivado. Moreover, these designs have lower area and higher frequency.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Journal of Parallel and Distributed Computing - Volume 106, August 2017, Pages 132-142
Journal: Journal of Parallel and Distributed Computing - Volume 106, August 2017, Pages 132-142
نویسندگان
Enrique De Lucas, Marcos Sanchez-Elez, Inmaculada Pardines,