کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
4951587 | 1441482 | 2017 | 10 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Delay analysis and optimization for inter-core interference in real-time embedded multicore systems
ترجمه فارسی عنوان
تجزیه و تحلیل تاخیر و بهینه سازی برای تداخل بین هسته در سیستم های چندگانه جاسازی شده در زمان واقعی
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
نظریه محاسباتی و ریاضیات
چکیده انگلیسی
The Worst Case Execution Time (WCET) is one of the most important performance metrics in real-time systems. With multi-core architectures becoming a trend in real-time systems, the WCET analysis is of great challenge, since multiple cores accessing shared hardware resources, such as cache and bus, may result in significant interference on them. In this paper, we propose a finer grained approach to analyze the inter-core interference(bank conflict and bus access interference) on multi-core platforms with the interference-aware bus arbiter(IABA) and bank-column cache partitioning, and our approach can reasonably estimate interference delays based on request timing. Moreover, we optimize bank-to-core mapping to reduce the interference delays, and develop an algorithm for finding the best bank-to-core mapping. The experimental results show that our interference analysis approach can improve the tightness of interference delays by 18.36% on average compared to Upper Bound Delay(UBD) approach, and the optimized bank-to-core mapping can achieve the WCET improvement by 8.93% on average.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Journal of Parallel and Distributed Computing - Volume 103, May 2017, Pages 77-86
Journal: Journal of Parallel and Distributed Computing - Volume 103, May 2017, Pages 77-86
نویسندگان
Zhihua Gan, Mingquan Zhang, Zhimin Gu, Hai Tan, Jizan Zhang,