کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
4951599 1441476 2017 8 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Matching circuits can be small: Partial evaluation and reconfiguration for FPGA-based packet processing
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر نظریه محاسباتی و ریاضیات
پیش نمایش صفحه اول مقاله
Matching circuits can be small: Partial evaluation and reconfiguration for FPGA-based packet processing
چکیده انگلیسی
Network functions like routing or firewalling require specialized hardware such as FPGAs to process packets at high rates. Such hardware must be fast enough to process packets at line rate, and it must be programmable to update the installed packet processing policy. However, these goals are conflicting because a generic programmable circuit must provide sufficient resources to support a wide range of policies, which can lead to unused circuitry and low clock rates. Also, it misses logic optimization opportunities with regard to the structure of the installed policy. In this work, we investigate the optimization potential of policy-specific generated network processing circuits. Using the example of router forwarding information bases (FIBs), we demonstrate that FIB-specialized circuits need significantly fewer logic resources than equivalent generic forwarding circuits. In combination with the partial reconfiguration capability of FPGAs, we obtain efficient low-latency forwarding engines whose matching circuitry can be replaced on demand.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Journal of Parallel and Distributed Computing - Volume 109, November 2017, Pages 42-49
نویسندگان
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