Fabrication of a nano-scaled tri-gate field effect transistor using the step-down patterning and dummy gate processes

The process sequence and device performances of the three-dimensional tri-gate field effect transistor (TGFET) were reported, where a fin-shaped Si channel with a 20 nm channel width and an 80 nm fin height was fabricated using the conventional i-line stepper, assisted by the double hard mask step-down (DHMSD) lithography process. The channel length was 150 nm. An atomic-layer-deposited Al2O3 film with an equivalent oxide thickness of 1.9 nm and a TiN layer grown through another atomic layer deposition process were adopted as the high-k and metal gate, respectively, using the dummy gate process. The device performance was compared with that of the planar FET simultaneously fabricated on the same Si wafer. The ion implantation and Ni-silicide processes were also optimized for this process sequence. Both n- and p-type devices were fabricated. The TGFET showed a high on/off current ratio of ~ 106, a low subthreshold swing of 105 mV/dec for the n-type device, and a small drain-induced barrier lowering of 30 mV for the n-type device, which were remarkably improved device performances compared with the planar FET device. These improvements were due to the improvement of the electrostatic control of the fin-shaped channel by the tri-gates, which coincides with the theoretical expectation and previous experiment results. Nevertheless, the p-type devices showed inferior performances compared with the n-type devices due to the excessive dopant diffusion from the source and drain regions into the channel.