Trapping analysis and countermeasure for arsenic auto-doping in 40-nm epitaxial diode arrays and CMOS integration

In this work, a methodology to analyze trapping mechanism of As auto-doping has been presented in the epitaxial diode array and CMOS integration. With a temperature-pressure optimization in three-step silicon epitaxial growth being proposed, As trapping mechanism has been revealed and auto-doping effect has been suppressed efficiently. Most importantly, the shifting CMOS devices are adjusted to meet the 40-nm Wafer Acceptance Test (WAT) target value according to technology computer aided design (TCAD) simulation results. High-resolution transmission electron microscopy (HRTEM) image reveals that the periodical lattice structure of silicon epitaxy has been formed in this three-step epitaxial growth. As surface and bulk auto doping profiles of in diode array and CMOS regions have been investigated by secondary ion mass spectroscopy (SIMS). It demonstrated that As auto-doping effect can be suppressed by higher temperature of 1100 ℃ and lower background partial pressure of 10 Torr in the capping and main epitaxy deposition respectively, without compromising epitaxial film quality. According to the optimal diode array process, normalized buried N+ layer (BNL) doping level of 4.5 has been employed to achieve lower word-line (WL) series resistance of 60Ω/sq, and higher on-current density of 1.47×107A/cm2 in 16×16 bits 4F2 diode array.