Design strategies for ultra-low power 10Â nm FinFETs

- 3D TCAD simulations are performed for 20 nm gate length, 10 nm node bulk n-FinFETs.
- Effects of punch-through stop and source-drain junction placement are investigated.
- The results show that the FinFETs can be designed for ultra-low power applications.

In this work, new design strategies for 10 nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20 pA/μm < IOFF < 50 pA/μm) and ultralow power (ULP) (IOFF < 20 pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (IOFF), transconductance (gm), gate capacitance (Cgg) and intrinsic frequency (fT). It is shown that the gate length of 20 nm for the 10 nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.