Characterization and modelling of layout effects in SiGe channel pMOSFETs from 14Â nm UTBB FDSOI technology

The introduction of strained channel is mandatory to achieve high performance in Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI) technology. Especially, compressive SiGe channel has been demonstrated to enhance hole mobility and therefore pMOSFETs drive currents. At the same time, the performance gain induced by this mechanical stressor comes along with layouts effects. In this study, we characterize experimentally the impact of the active region dimensions and shape on the threshold voltage and linear drain current of SiGe channel pMOSFETs directly on insulator fabricated for the 14 nm technology node. The pMOS threshold voltage increases by 105 mV for a gate-to-STI distance of 80 nm compared to 980 nm while IODLIN decreases by 51%. An analytical model is proposed to reproduce the layout dependences. The model is based on the stress profile, taking into account both the stress from the SiGe channel and from SiGe source/drain. It reproduces the experimental data with a good accuracy in the cases of symmetric and asymmetric layouts, provided a typical relaxation length of 112 nm is used. Finally, a special attention is paid on multifinger transistors, since they are widely used in standard cells designs.