Realization of Silicon nanotube tunneling FET on junctionless structure using single and multiple gate workfunction

In this paper, we demonstrate the operation of a Silicon Nanotube Tunneling FET on junctionless structure using 3D numerical simulations. P-I-N band structure thereby the tunneling operation is achieved by placing side gates and applying appropriate side gate biases. Single work function, with the same main and side gates workfunctions and multiple workfunction, with different main and side gates workfunctions are explored to achieve Tunneling FET. ON current, OFF current, Sub-threshold swing, Threshold voltage, trans-conductance and unity gain frequency are extracted for both single and multiple gate workfunctions based devices and compared with the conventional Silicon nanotube tunnel FET. For the same OFF current, the proposed devices show better performance with respect to ON current and sub-threshold swing compared to the conventional Silicon nano tube tunnel FET.