کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
5010424 | 1462207 | 2016 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Layout optimization of GGISCR structure for on-chip system level ESD protection applications
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موضوعات مرتبط
مهندسی و علوم پایه
سایر رشته های مهندسی
مهندسی برق و الکترونیک
پیش نمایش صفحه اول مقاله
چکیده انگلیسی
To improve the holding voltage, area efficiency and robustness, a comparative study on single finger, 4-finger and round shape layout of gate-grounded-nMOS incorporated SCR (GGISCR) devices are conducted. The devices were fabricated with a commercial 0.35 μm HV-CMOS process without any additional mask or process modification. To have a fair comparison, we develop a new Figure-of-Merit (FOM) modeling for the performance evaluation of these devices. We found that the ring type device which has an It2 value of 18.9 A is area efficient and has smaller effective capacitance. The different characteristics were explained with the different effective ESD currents in these layout structures.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Solid-State Electronics - Volume 126, December 2016, Pages 152-157
Journal: Solid-State Electronics - Volume 126, December 2016, Pages 152-157
نویسندگان
Jie Zeng, Shurong Dong, Hei Wong, Tao Hu, Xiang Li,