کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
538421 871090 2013 10 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
FPGA-based hardware acceleration for local complexity analysis of massive genomic data
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
FPGA-based hardware acceleration for local complexity analysis of massive genomic data
چکیده انگلیسی

While genomics have significantly advanced modern biological achievements, it requires extensive computational power, traditionally employed on large-scale cluster machines as well as multi-core systems. However, emerging research results show that FPGA-based acceleration of algorithms for genomic applications greatly improves the performance and energy efficiency when compared to multi-core systems and clusters. In this work, we present a parallel, hardware acceleration architecture of the CAST (Complexity Analysis of Sequence Tracts) algorithm, employed by biologists for complexity analysis of protein sequences encoded in genomic data. CAST is used for detecting (and subsequently masking) low-complexity regions (LCRs) in protein sequences. We designed and implemented the CAST accelerator architecture and built an FPGA prototype, with the purpose of benchmarking its performance against serial and multithreaded implementations of the CAST algorithm in software. The proposed architecture achieves remarkable speedup compared to both serial and multithreaded software CAST implementations ranging from approx. 100x–5000x, depending on the system configuration and the dataset features, such as low-complexity content and sequence length distribution. Such performance may enable complex analyses of voluminous sequence datasets, and has the potential to interoperate with other hardware architectures for protein sequence analysis.


► A hardware accelerator for complexity analysis of genomic data is proposed.
► An FPGA-based prototype of the proposed architecture is implemented and tested against software implementations.
► Speedups of 100x–1900x over single and multi-threaded software implementations.
► The proposed system is fully scalable and each instance occupies only 10% of a Virtex-5 LX110T FPGA.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 46, Issue 3, June 2013, Pages 230–239
نویسندگان
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