An FPGA based human detection system with embedded platform

• Focusing on speeding up computation of the machine learning based human detection system.
• The proposed HOG accelerator contains gradient calculation and histogram accumulation circuit modules.
• The performance error between with and without HOG accelerator appears about 0.1–0.4%.
• The completed FPGA based human detection system processes about 1075 detecting windows in a second.

Focusing on the computing speed of the practical machine learning based human detection system at the testing (detecting) stage to reach the real-time requirement in an embedded platform, the idea of iterative computing HOG with FPGA circuit design is proposed. The completed HOG accelerator contains gradient calculation circuit module and histogram accumulation circuit module. The linear SVM classification algorithm producing a number of necessary weak classifiers is combined with Adaboost algorithm to establish a strong classifier. The human detection is successfully implemented on a portable embedded platform to reduce the system cost and size. Experimental result shows that the performance error of accuracy appears merely about 0.1–0.4% in comparison between the presented FPGA based HW/SW co-design and the PC based pure software. Meanwhile, the computing speed achieves the requirement of a real-time embedded system, 15 fps.

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