Peeling model of dielectric film including low-k material on wafer edge

• We clarified a peeling mechanism of multi layer films including low-k material.
• The peeling increases when core particles present under the base layer.
• The peeling increases as the low-k film thickness increased.
• The peeling decreases by plasma treatment of low-k film.
• The peeling is deeply related to the roughness or stress of the underlying layers.

This study explores and clarifies a peeling model of multilayered films caused by a stacked low dielectric constant (low-k) material on a wafer edge. The dielectric is deposited by chemical vapor deposition (CVD) and composed of a low-k film (methyl-doped silicon oxide) embedded between plasma-enhanced CVD (PE-CVD) SiO2 layers, which consist of a cap (upper) and base (bottom) layer. We found that peeling occurs from the cap layer during thermal treatment and is accelerated when core particles (CP) are present under the base layer at the wafer edges. In addition, the peeling increased as the low-k film thickness increased. However, the peeling decreased after plasma treatment. Based on these findings, we propose a possible model of peeling.

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