کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
539250 1450374 2013 7 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer-level underfill
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer-level underfill
چکیده انگلیسی

With the impressive size shrinkage of advanced transistors and Cu/low-k interconnect systems, the introduction of through-silicon via integrated with three-dimensional (3D) chip-stacking approaches has become one of the major packaging technologies to meet the desired requirements of multifunctionality. The use of microbump (μ-bump) interconnected silicon chips to ensure the reliability of the interconnections is regarded as a critical issue that must be resolved. In this research, wafer-level underfill (WLUF) joined with flip-chip technology are proposed, and a nonlinear finite element analysis, combined with a process-oriented simulation technique, is used to investigate the packaging assembly effect of the WLUF thermal-compressive process. The stress predictions during the temperature cycling test is also systematically explored. The proposed simulation methodology is successfully validated through comparison with experimental data. The analytical results indicate that both the assembly and thermomechanical reliabilities of μ-bumps are determined by the arrangement of the μ-bump arrays. Consequently, the optimal designs of μ-bump layouts within the chips must be seriously considered, given that silicon chips thinner than 100 μm are assembled in 3D advanced packages.

Figure optionsDownload as PowerPoint slideHighlights
► 3D-ICs assembly reliability is enhanced by proposed wafer-level underfill technology.
► Assembly effect is estimated by process-oriented finite element simulation.
► Testing and simulated results under thermal cycling loads are compared.
► Bonding force is a key factor to chip assemblies with the use of present underfill.
► Layout of micro-bumps in thin chips needs to be carefully designed.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronic Engineering - Volume 107, July 2013, Pages 107–113
نویسندگان
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