Device simulation of a novel strained silicon channel RF LDMOS

In this paper we propose a novel RF LDMOS structure which employs a thin strained silicon layer at the top of both the channel and the N-Drift region. The strain is induced by a relaxed Si0.8Ge0.2 layer which sits on top of a compositionally graded SiGe buffer. We have used a 2D device simulator to investigate improvements in the output characteristics of the device including saturation and linear transconductance, current drivability, cut off frequency and the on resistance. Furthermore we have examined the capacitance voltage behavior of the proposed strained silicon LDMOS device and have compared it with that of the conventional LDMOS device. It is observed that the gate capacitance increases in strong inversion with strain, but remains relatively unaffected in depletion and accumulation modes of the device operation.

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► Novel strained silicon LDMOS structure has been proposed.
► Its output characteristics have been compared with that of a conventional LDMOS device.
► Strain layer leads to a great improvement in the device performance (Table 1).
► Capacitance–voltage characteristics of the proposed device is examined.