Phase Change Memory lifetime enhancement via online data swapping

• In this paper we propose an online data-swapping (ODS) scheme to prolong PCM lifetime. The main idea behind ODS is dividing each line of memory to chunks of data and then swap incoming write request between predefined sets of chunks to reduce the number of bit flips.
• In order to employ ODS in main memory, a circuitry is added between last level cache and main memory to perform the swapping process.
• Hence, ODS requires the addition of metadata information for each chunk of data. Due to aggressive updates in such metadata information, they are stored in DRAM memory.
• Experimental results carried out on PARSEC 3.0 [24] demonstrate that ODS improves the endurance of PCM based main memory endurance by about 48% and reduces its power consumption by approximately 46%.
• However, the average memory access is increased by 1% due to the added circuitry.

As DRAM technology is facing scalability limitations due to its excessive leakage power in nano-scale technologies, various non-volatile memory technologies have been emerged to replace it in memory hierarchy. Among these technologies, Phase Change Memory (PCM) is a promising technology for main memory due to its near-zero leakage power, higher density, non-volatility and soft error immunity. However, its major drawbacks, including high write energy and limited write endurance, have prevented its usage as a drop-in replacement of DRAM technology. In this paper, we propose a technique to swap data between memory lines with goal of reducing bit flips. The proposed swapping technique finds the best place to write a chunk of data among a limited set of lines to minimize number of bit flips. The proposed swapping operation works online i.e, does not require any data profiling. Moreover, it does not require major modifications of existing solutions and works only by the addition of a proposed circuitry. It is remarkable that, this technique is additive to various other architectures aiming at PCM lifetime enhancement. Experimental results carried out on a quad core CMP system show that the proposed technique prolongs PCM main memory lifetime by 48% which is achieved at the price of 1% and 2% overhead in read and write latencies respectively.