Electrical and reliability characterization of CuMn self forming barrier interconnects on low-k CDO dielectrics

PVD CuMn self-forming barrier (SFB) approach was investigated on 300 mm wafers as an alternative to conventional PVD Ta/Cu metallization. Cu fill on very aggressive dual damascene features targeted for beyond 32 nm node was evaluated along with integrated electrical and reliability performance on low-k (k = 2.6) interlayer dielectric (ILD).

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