Reducing random-dopant fluctuation impact using footer transistors in many-core systems

• The paper addresses the impact of process variation on core-speed in multi-cores.
• A new technique using multi-Vt is proposed to reduce RDF impact on delay and power.
• Our method lowers dopant density and then compensates Vt using a footer transistor.
• There was a 25–17% reduction in the total standard deviation of core-speed variation.
• Energy saving of 30 STG mapped on many-core improved by 5%, and performance by 6%.

Process variation creates core-speed discrepancy among the core in a many-core platforms. Random variation is one of the important components that contributes into core-speed discrepancy. In this paper, we propose a novel technique that uses footer transistors to reduce the impact of random process variation on delay and power in a many-core platform. Process variation is due to many fundamental deficiencies, impurities, and imperfections during the fabrication process at the nano-scale technologies. The results of this variation have a direct impact on two key parameters of the CMOS transistor: threshold voltage and gate length, which have major implication on the core speed and power. The random component of this variation is mostly attributed to the random-dopant fluctuation, which results in threshold voltage discrepancy among the cores. The proposed technique reduces the random dopant fluctuation by lowering the dopant density and then compensating the threshold voltage using a footer transistor. The results show a reduction of the total standard deviation from 25% down to 17% using the proposed method. Furthermore, the average energy saving of 30 different applications mapped on a many-core platform is improved by around 5%, and the performance by around 6%.