An integrated electroless nickel plating process for fabrication of CMOS-MEMS probe chip

• We adopt the post-CMOS procedure to develop a novel probe chip.
• The procedure includes lithography, EN plating, grinding, and etching.
• The chip designs a TSV structure to combine with the multi-layer interconnections.
• TSVs can simplify the wiring layout between probe heads and other external devices.
• Passive components or circuits can be possibly integrated with CMOS chips.

This study designs a CMOS-MEMS probe chip and fabricates it using the 0.35 μm CMOS process of the Taiwan Semiconductor Manufacturing Company (TSMC). The post-CMOS procedure is a Micro-electromechanical system (MEMS) technology that involves steps such as lithography, electroless nickel (EN) plating, grinding and dry etching. The probe chip has a through-silicon-via (TSV) package structure combination with the multi-layer interconnections within CMOS processes, which simplifies the wiring layout and improves the connectivity between the probe heads and external devices. In addition, passive components or circuits are inherently integrated with CMOS chips to increase the frequency bandwidth and measurement quality. Finite element analysis is used to design the probe shape and the LIGA-like thick photoresist process using EN plating techniques is used to fabricate the probes. The Ni-P alloy is applied to the probe to thicken and strengthen the cantilever part of the probe. The different deposition areas for several types of cantilever probes on the same chip fabricated by EN plating using different growth rates result in unequal probe heights. Therefore, polishing each plated layer of the probe is a necessary step to guarantee the co-planar surfaces. Finally, the probe structures are suspended using dry etching (RIE, ICP-RIE) and the probe cantilevers have no warp.

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