A thermal–mechanical coupled finite element model with experimental temperature verification for vertically stacked FPGAs

Back end of line 3D integration of dies is a promising technology that can allow for considerable boost in inter-chip communication and reduction in form factor of a package. This can result in, however, high die temperatures, particularly for multi-tier FPGAs, due to the high density of power dissipating circuits. Therefore, to design thermally aware multi-tier FPGAs, there is a need to first understand the relationship among circuit architectures, toggle rates, layout, clock frequency, I/O behavior, power, temperature, thermal stress, and thickness of inter-die substrates. This study investigated the relationship among these parameters as tested on a Spartan 3E-250K FPGA. The power-temperature simulations have been conducted on a model built in ANSYS finite element package. The model predictions have been verified by thermocouple-measured case temperatures. The verified model has been extended to predict the temperature and stress distributions for a 2-tier, stacked package.

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