Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics

Quantized threshold voltage (VTH) relaxation transients are observed in nano-scaled field effect transistors (FETs) after bias temperature stress. The abrupt steps are due to trapping/detrapping of individual defects in the gate oxide and indicate their characteristic emission/capture times. Individual traps are studied in n-channel SiO2/HfSiO FETs after positive gate stress to complement previous studies performed on SiO(N). Similarly to single SiO(N) traps, strong thermal and bias dependences of the emission and capture times are demonstrated. The high-k traps have a higher density but a reduced impact on VTH due to their separation from the channel.

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