MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO2 (t-ZrO2) film with permittivity (κ) of 36.2 was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO2. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO2 gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance–voltage (C–V) characteristics. By passivating leaky channels derived from grain boundaries with NH3 plasma, good leakage current of 4.8 × 10−8 A/cm2 at Vg = Vfb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.

The gate stack used in this work includes a thin SiON layer and a ZrO2/Ge/ZrO2 laminate. The effects of thermal annealing on X-ray diffraction pattern and capacitance characteristics are presented.Figure optionsDownload as PowerPoint slideHighlights
► A Ge-stabilized tetragonal ZrO2 was formed by annealing a ZrO2/Ge/ZrO2 laminate.
► A Ge-stabilized tetragonal ZrO2 demonstrates a permittivity of 36.2.
► Tetragonal ZrO2/SiON shows EOT of 1.75 nm with good interfacial quality.
► Grain boundary induced leakage current can be alleviated by NH3 plasma passivation.
► The gate stack shows good leakage current and desirable reliability performance.