|کد مقاله||کد نشریه||سال انتشار||مقاله انگلیسی||ترجمه فارسی||نسخه تمام متن|
|540528||871316||2011||4 صفحه PDF||سفارش دهید||دانلود رایگان|
Threshold voltage (VT) and mobility (μ) shifts due to process related variability and Negative Bias Temperature Instability are experimentally characterized in pMOSFETs. A simulation technique to include the time-dependent variabilities of VT and μ in circuit simulators is presented and used to evaluate their effects on CMOS inverters performance. The results show that mobility degradation under NBTI stresses could have to be considered for the evaluation of the circuit performance after device aging.
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Journal: Microelectronic Engineering - Volume 88, Issue 7, July 2011, Pages 1384–1387